Partially Redundant Fence Elimination

for x86, ARM and Power processors

In this project we study how partial redundancy elimination (PRE) can be instantiated to perform provably correct fence elimination for multi-threaded programs running on top of the x86, ARM and IBM Power relaxed memory models. Currently we have implemented our algorithm in the backends of the LLVM compiler infrastructure.

Resources:

  • Partially Redundant Fence Elimination for x86, ARM and Power processors, in CC'17 [.pdf];
  • patch against LLVM: [patch] and [readme];
  • LibKPN sources are available here;
  • experimental measures on x86_64 and IBM Power7.

    People:

  • Robin Morisset
  • Francesco Zappa Nardelli

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