Idemoptent store introduction

atomic_int a_7;
uint16_t g_10;

void func_1 () {
  for (; a_7.load () <= 0; a_7.store (a_7.load () + 1) )
    for (; g_10; g_10--) 
        ;
}

The reference trace for func_1 is:

     a_7   0  4   ALoad
RaW* g_10  0  2   Load
     a_7   0  4   ALoad
     a_7   1  4   AStore
                  Flush
     a_7   1  4   ALoad
The trace generated by gcc --param allow-store-data-races=0 -O2 (or -O3) is:
     a_7   0  4   ALoad
     g_10  0  2   Store
     a_7   0  4   ALoad
     a_7   1  4   AStore
                  Flush
     a_7   1  4   ALoad
The optimiser introduced the idempotent store Store g_10 0 2, which cannot be observed by a non-racy context. However it is unclear if it is a good idea to let a compiler introduce indempotent writes.

Current status: don't fix.


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